Companies rely on verification engineers to ensure that their products work as intended. Prepare to answer questions that will assess your ability to design and implement product testing methods. Expect the interviewer to evaluate your communication and documentation skills – these are essential when working with product designers.
You have 2 pieces of rope, each of which burns from one end to the other in 30 minutes (no matter which end is lit). If different pieces touch, the flame will transfer from one to the other. You cannot assume any rope properties that were not stated. Given only 1 match, can you time 45 minutes?
PHONE : 1. Pass by value/ pass by reference. Write a function to swap 2 variables - ll u use pass by value or reference ? 2. Do the same to swap 2 objects (how does it change) 2. Detect 11010 sequence with moore and mealy state machines. 3. Use of const ? What ll happen if you declare above 2 objects as const. 4. Explain NB assignment and blocking assignment. About event regions. 5. Fibonacci -- iterative solution and recursive solution. 6. Disadvantages of a recursive solution. 7. Output of this code fragment : reg a,b,c,d,w; assign w = a; initial begin a = 2; c=5; b<=c; a=5; end what is output of all registers. 8. Explain RISC pipeline. What is the problems. 9. Explain about uvm driver etc. ONSITE : round 1: Round Robin Arbiter Design round 2 : (1) Given a stack class implementation (LIFO) - there are 3 methods - push(), pop(), isempty(). Write a class using objects of given class to implement a FIFO. (2) Make best performance Implement the dist functionality in c++. Given a set of weights mimic to provide randomization skewed to the specification (Basically, write a function that would do something similar to a 'dist' in system verilog). round 3 : Given a divide by 3 state machine. Implement a divide by 5 statemachine. How many vectors are needed to verify it. So the circuit takes serial bit inputs and asserts if the number is a multiple of 3 or 5. round 4 : Circuits project. Basic pipeline architecture. Design a pipeline for a histogram processor. In every cycle we get an instruction (CLR, ADD INCR). Handle dependencies using bypass. round 5 : Given a producer and consumer. They are clocked with the same clock. Producer produces 80 writes for 100 clocks (no random). Consumer reads 8 times per 10 clocks. Find the FIFO depth. Write RTL and verify.
Create a 8 input AND gate using 3 4:1 muxes
Describe a function to check if an integer is a power of 2.
You have seven stones and a weighing scale. Six of the stones are equal in weight and one is lighter. How will you figure out which one is lighter ? Minimum tries required to do so ?
how to find the second smallest number out of iven n integers
How would you verify a 3 bit and 64 bit adder? Would you adopt the same strategy?
Describe a circuit that implements the following truth table using only NAND gates. A B OUT 0 0 1 0 1 1 1 0 0 1 1 1
Calculate fifo depth for following data rate Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s) Outgoing Data= 8 DATA/10 Clock. Burst size = 160
is run phase top down/bottom up
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