1. Explain SRAM working and Noise margins of it.
2. How does PVT variation affect SRAM access times and NM.
3.Concept of Setup time and Hold time. How to fix it in Si validation.
4.Leakage current of MOSFET. How does it scale with Length, Vth and Temperature. Techniques to reduce leakage current of MOSFET (Multi Vt, DVFS, Body biasing, Header/Footer switch, Clock gating)
5. Where to use Header and Footer switch? Does FinFet has body biasing phenomenon to reduce leakage like conventional FETs.
6.Any experience with EM simulation, memory compiler design and Digital verification/STA.
