# 510

Asic Design Engineer interview questions shared by candidates

## Top Interview Questions

Sort: Relevance|Popular|Date
ASIC Design Engineer was asked...21 September 2010

### design a full adder with 2-1 mux

full adder can be got by 2 half adders and one OR gate; one half adder can be got by XOR, AND. Therefore, we need only OR, AND, XOR. All these three gates can be got by using MUX.? Less

sum = a xor b xor cin carry = (a xor b) cin + ab You can easiy make XOR, OR AND, NOT using 2:1 mux. So 8 mux ?!? Less

if Mux(I1,I2,S) is a 2x1 mux module, then Sum = Mux( (Mux(C,C',B), Mux(C',C,B), A) which requires 3 2x1 mux. Carry = Mux( (Mux(0,C,B), Mux(C,1,B), A) which requires 3 2x1 mux. Less

### design a combinational circuit which counts the number of 1s in a 7-bit input .

It can be done by two ways Clocked Circuit: Use a one bit adder and a register. Output of the register acts as 2nd input to the adder. Half adder can also be used. Combinational Circuit: We can do it in 4 full adders. For the adders A and B, let 6 bits be the inputs. For adders C, use the 7th bit and Carry of adder A and B. Adder C gives sum as bit 0. For adder D, use carry from all three adders. The sum is bit 1 and carry is bit 2. Less

@Akash, Adder C should be the 7th bit and the sum of adder a and b right? not carry Less

depending on resource and timing constraints, you can use a cascade of adders, where you repeatdly add each bit starting with bit 7 to each other. this is slow because the critical path is on the Cin -&gt; Cout. to improve, you can go further and use a 7bit decoder/any arrangement of decoder/column muxer + decoder for a lookup, which is essentially an SRAM array design to store this value so that next time you try to do this computation, you can directly access it. Essentially caching computation result. This requires extra circuitry overhead, but means you only have to compute the sums once. Less

### is there any benefit to use cache if there is read miss for every access?

you should probably think a little more about this problem before you just say there's no benefit, thought in most cases I do agree with u. you haven't said anything about write misses, and even though the delay contributed by them isn't as much as a read miss, i'd still mention it as a plus for having a cache, especially in write-back caches where you could potentially have a trace of just writes to locations brought in by your read misses, which means you get n number of cache write hits. Also make sure to mention ways to improve cache hit percentage by either increasing the cache size, changing the associativity of the cache, or by changing the compiler to optimize for the cache type (if we're talkin about an I-cache). Less

Is pattern is such that there would be miss on every access, then there would no benefit of having a cache for both read misses and write misses. If it's a read miss for a block, then there would also be a write miss for that same block. Could you be more specific as to how it would benefit to have cache in such a scenario? Less

The question doesn't say anything about writes. So even if every read is a miss, the cache will help in processor performance by providing write hits. It is very common that we read and update the same variable. For instance a++ or any operation of this sort. So cache is beneficial. Less

### How many data bits needed to represent A*B+C, all are 8 bit unsigned

15bits is enough [0, 2^16-2^8]; 15 bits can represent [0, 2^16-1].

16 bit. It is because the worst condition is 0xFF*0xFF+0xFF, it is 0xFF*0x100. Result is 0xFF00. Less

(2^8-1)*(2^8-1)+2^8&lt;2^8*2^8=2^16

### Complete the C function (body) that uses recursion to determine if the string is a palindrome

int isPalin(char *str){ int l = strlen(str); return isPalinHelper(str,0,l-1); } int isPalinHelper(char *str,int i,int j){ if(i Less

#include #include int palindrome(const char* head,const char* tail) { int val; if (head &gt;= tail) return 1; return (palindrome(head+1,tail-1) &amp;&amp; (*tail == *head)); } int check_palindrome (const char* str) { const char* tail = str + strlen(str) - 1; const char* head = str; return palindrome(head,tail); } int main(int argc, void* argv[] ) { if (check_palindrome (argv[1])) printf("true\n"); else printf("false\n"); } Less

bool palindrome(char* str, int len) { if(len&lt;=1) return true; if(len == 2) if(str[0] == str[1]) return true; return (str[0] == str[len-1]) &amp;&amp; palindrome(str+1, len-2); } Less

### Design a divide by 3 counter. Bonus for 50% duty cycle

I think this is the fastest way to do it. http://www.onsemi.com/pub_link/Collateral/AND8001-D.PDF Of course, I would not have been able to just innovate this in the blue in the middle of an interview tough... Less

is dual edge flip flop a kind of cheating?

Take 3 dual edge flip flops and create a Johnson's counter. The output will be divide by 3 with exactly 50% duty cycle Less

### Why setup in ICG is tough to solve?

Only half cycle is available to meet the timing of enable signal.

ICG are placed before sequential flop/latch. That's why compared to flop/latch, ICG get lesser clock period to meet setup timing on. + ICG has internal latch + clock gate thats why setup time is also more comparatively. Less

There's quite an extended back and forth in actual interviews for questions like this, so nothing quite like real practice. The Prepfully Nvidia ASIC Design Engineer experts have actually worked in this role, so they're able to do an honest-to-God accurate mock, which really puts you through the paces. prepfully.com/practice-interviews Less

### Suppose you have a 4-bit shift register made using D-type flip flops with a positive Clock-to-Q delay and a hold time of 0. Is it possible for this circuit to have hold time violations? Why?

it may have hold violations if clock skew is more than data path delay

Yes, the circuit can still have hold time violation. For a circuit having hold time = 0, it simply means that the data has to remain constant until the clock edge if not after it. So, if the data changes before the clock edge its setup and hold time at once :-) Less

No it can never have hold time violation since clk to q is +ive, that much delay will always be there so data will always remain constant till clk to q time. Less

### Design a circuit that would count 1 every time another counter counts from 0 to 255. One of the counter is working at higher frequency than the other.

f/256

if it is a design question, shouldn't we answer as below usa temporary variable with one bit additional to that of the counter and use it for incrementation. Then assign the msb to this low freq output and the rest to the original counter Less

f/8

### What would be behavior of a CMOS inverter if the nMOS and pMOS are interchanged?

It will act as a weak buffer

It will be an inverter with its high output being Vdd-Vtn and low output being Vtp. Thus a bad inverter !! Less

No. Mayank is right. It will act as a weak buffer with the high value being Vdd- Vtn and the low value being Vtp. Less

Viewing 1 - 10 of 510 Interview Questions

## See Interview Questions for Similar Jobs

physical design engineer