Interview process was very good . The questions was basically based on Verilog and system Verilog. Also some aptitude questions. It was good and very easy. If we study basic verilog questions then we will be able to perform the interview very well
I applied through a recruiter. I interviewed at Tessolve (Bengaluru)
Interview
two technical round followed by hr . they are more checking my sv , uvm knowledge and current project contribution. based on scenario we have to explain the uvm tb creation and verification clousure
I applied online. I interviewed at Tessolve (Bengaluru)
Interview
3 steps step1 : Offline test Step2 : face to face technical round step3 : HR round offline test is like exam only there will be questions related to circuit theory and CMOS fabrication process and layout depend effects
