I have at least one 45–60 min technical interview over phone or video. Common themes: Core digital logic: latches vs flip-flops, where you’d use latches, timing issues, counters, FSMs, adders, muxes, etc. Timing: setup and hold time, what causes violations, temperature/voltage effects, metastability, CDC basics, how to prove a chip has setup-time issues. HDL & RTL: Verilog/VHDL coding for simple blocks (D flip-flop, counters, etc.), blocking vs non-blocking assignments, continuous vs procedural assignment, synthesis basics. Sometimes basic analog/CMOS even for a “digital” role: CMOS inverter, simple gate schematics with PMOS/NMOS, NOT gate transfer characteristics, power in a resistor,