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      Analog Bits

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      CMOS Mixed Signal Circuit Design Engineer Interview

      30 Jan 2017
      Anonymous interview candidate
      San Francisco, CA
      No offer
      Neutral experience
      Average interview

      Application

      I applied through a recruiter. The process took 2 days. I interviewed at Analog Bits (San Francisco, CA) in Mar 2015

      Interview

      I didn't make it passed the phone interview. The man who interviewed me was very polite - I think he was a different person than the one who did phone interviews with other people on here - but I failed the last question, which is the same one everyone else on here mentioned. I can't remember it exactly but I've come back to see if I can answer it. I'll update if I figure out how to explain it.

      Interview questions [1]

      Question 1

      Mobility questions, how to build a NAND and NOR gate, and the one I failed was about a transistor in cutoff where you need the drain voltage.
      1 Answer

      Other CMOS Mixed Signal Circuit Design Engineer interview reviews for Analog Bits

      CMOS Mixed Signal Circuit Design Engineer Interview

      24 Aug 2012
      Anonymous interview candidate
      Mountain View, CA
      No offer
      Neutral experience
      Average interview

      Application

      I applied online. The process took 1 day. I interviewed at Analog Bits (Mountain View, CA) in Jun 2012

      Interview

      The process begins with a phone interview with some general questions about CMOS transistors. Some of the questions require grabbing a pencil and a piece of paper. The answers that you provide are submitted to the hiring manager, who then decides whether you will be called back for an on-site interview.

      Interview questions [2]

      Question 1

      How would you size the NMOS and PMOS transistors in an inverter to obtain equal rise and fall times?
      2 Answers

      Question 2

      How would you draw the CMOS schematic for a 2-input NAND gate? What would the pull-up and pull-down networks look like? If VDD and VSS are switched, what gate is formed?
      3 Answers
      2

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